1. Technical Field
Exemplary embodiments of the present invention relate to a method of programming a semiconductor memory device.
2. Related Art
Industrial and commercial demands for semiconductor memories capable of electrically programming and erasing, and reserving data without power supply are increasing. Also, higher integration density of memory cells has been dramatically advanced for the purpose of larger data capacity. One of these semiconductor memories is called a nonvolatile memory device. A nonvolatile memory device is generally equipped with a plurality of cell strings, each of which is formed of a plurality of memory cells coupled in series.
FIG. 1 depicts a section of a cell string 100 in a semiconductor memory device.
As depicted in FIG. 1, in the cell string 100 of the semiconductor memory device, 32 memory cells C0 to C31 are serially connected between a drain selection transistor DST and a source selection transistor SST.
The semiconductor memory device may include a plurality of the cell strings 100. The drain selection transistors DST of the cell strings 100 are coupled respectively to bit lines BL. The source selection transistors SST of the cell strings 100 are commonly coupled to a common source line SSL.
The memory cells C0 to C31 are coupled respectively to word lines WL0˜WL31.
A plurality of the cell strings 100 constitute a memory cell array (not shown) that is included in the semiconductor memory device.
Each memory cell is selected by the word and bit lines corresponding thereto.
Each memory cell is constructed by including a floating gate FG and a control gate CG.
In each memory cell, a threshold voltage is elevated when electrons are charged at the floating gate FG. Performing an operation to elevate the threshold voltage of the memory cell is referred to as programming.
The semiconductor memory device is programmed on a page-by-page basis. A voltage for programming, i.e., a program voltage Vpgm, is applied to the memory cells that are coupled to the word lines in a page.
When programming the memory cell C0 coupled to the word line WL0, the program voltage Vpgm of a high level is applied to the word line WL0, while a pass voltage Vpass is applied to the other word lines WL1 to WL31.
While programming in this manner may be performed to any of the memory cells, several memory cells should be maintained in erased states, so that not all of the memory cells belonging to a single page are programmed.
However, since gates of the memory cells are commonly coupled to one word line, the program voltage Vpgm is also applied to the memory cells that should be held in erased states. For that reason, program inhibition is needed to prevent the memory cells, which are to be kept in erased states, from being programmed even when the program voltage Vpgm is applied to their gates through the word line.
For program inhibition, a technique called self-boosting has been conventionally used in the semiconductor memory device.
FIG. 2 is a timing diagram showing a self-boosting scheme of a semiconductor memory device.
Below, FIG. 2 is described with reference to FIG. 1, and it is assumed that the cell string is to be program-inhibited.
If the memory cell C0 of the cell string 100 is selected to be program-inhibited, the bit line BL is precharged to a level of a power voltage VCC before applying a program voltage or pass voltage to the word lines. At this time, the power voltage VCC is also applied to a drain selection line DSL and 0V is applied to a source selection line SSL.
If the pass voltage Vpass is applied to all of the word lines, a voltage across the memory cells, i.e., a channel voltage of the cell string, slowly increases as the pass voltage Vpass increases. And, responding to an increase of the voltage applied to the word line WL0, the channel voltage of the cell string is proportionally elevated together. For example, with the pass voltage Vpass at about 10V and the program voltage Vpgm at about 18V, the channel voltage of the cell string rises to about 8V.
Where 18V is applied to the control gate CG of the memory cell C0 and the channel voltage is 8V, a voltage gap of about 10V between the control gate CG and the channel is generated. This voltage gap of about 10V is not enough to charge the floating gate FG, and thus, the memory cell C0 is prevented from being programmed. Such a manner of program-inhibiting by increasing the channel voltage is known as a self-boosting scheme.